The present invention concerns an improvement to a video display terminal which is communicating with a data processing system.
It is known in the data processing arts to provide a multi-terminal data processing system in which a central processor and large central memory are shared by a number of intelligent terminals. User application programs and data are stored in the central memory. The central processor provides time-multiplexed access to the central memory by the terminals and may provide inter-terminal communications. Each intelligent terminal contains a keyboard for the entry of data and commands and a video display unit for displaying information to the user.
In such a system it is desirable to minimize the time that the central processor spends servicing each terminal, since by minimizing this time the size of the central processor may be kept relatively small. Alternatively, relatively more terminals may be serviced from the central processor.
It is known to provide "intelligence" at each terminal in the form of one or more terminal processors, terminal memories, and associated circuitry, in order to reduce the workload on the central processor. The terminal processor ordinarily requires at least some terminal memory to store routines and data to perform its various functions, which may include power-up and boot-loading, keyboard input, video display, printing, and communicating.
To reduce the workload on the terminal processor, it is known to improve terminal processor throughput by providing a separate video memory for storing data to be displayed on the screen. This avoids the necessity of the terminal processor sharing its memory workspace with the video display memory and consequently losing bus cycles every time a display memory access is made. By providing a separate video display memory, the terminal processor does not lose any bus cycles during screen refresh operations.
In the data processing system just described it is of course necessary to update the information stored in the video memory from time to time in order to update the information displayed on the screen. Since the video memory contents are accessed during screen trace time--i.e., when information is provided to the screen video circuits for display on the video screen--the only time available in which to update the video memory contents without introducing screen flicker is during screen retrace--i.e., when the CRT beam is retracing to its initial position. The screen retrace time is very short relative to the terminal processor interrupt response time and bus cycle time.
It is known in the prior art to utilize the video memory in an interleaved mode. The video memory is divided into two interleaved portions. As one portion is being accessed to refresh the screen, the other portion can be accessed by the terminal processor to update the information stored in the video memory. However, the interleaved memory technique has the disadvantage that two separate data busses are required on the circuit board containing the video generator circuitry. This increases the I/O pin count and circuit complexity and correspondingly increases the costs of the components and circuit packaging.
Thus there is a need for a technique for accessing the video memory for screen refresh and updating purposes which does not require interleaved memory but can utilize a single, integrated memory and which is fast enough to keep up with the terminal processor data rate and yet update the video memory only during screen retrace time.
The present invention provides the above advantages. In addition, the video update FIFO register of the present invention permits scrolling of either an entire line or of just a line segment through the use of the video memory controller (VMC) hardware circuitry primarily. Whereas scrolling of a line or line segment is known in the prior art, such is ordinarily accomplished primarily by the terminal processor using software routines which tie up the terminal processor. Thus the scrolling technique offered by the present invention has the advantage of easing the workload of the terminal processor for other tasks.
The present invention also enables either an entire line or merely a line segment to be "filled" with any selected character in response to a single terminal processor command.
In addition, the video update FIFO register of the present invention has the capability of reading any desired location within the video memory for diagnostic purposes and providing the contents of such location for inspection by the terminal processor. This mode can also be used to provide a blinking cursor in each of several independent video screen display areas.
The present invention provides the above-mentioned advantages by providing a 3-stage FIFO register between the terminal processor and the video memory. Each stage may, for example, comprise a three-byte word, each byte comprising 8 bits. The FIFO buffers the relatively steady stream of update information coming from the terminal processor and dumps it into the video memory during each screen retrace time.
The FIFO register responds to various terminal processor commands, one of which is to copy a line or line segment over another line or line segment, in effect "scrolling" the information appearing on the screen. An entire line or merely a line segment may be scrolled in response to a single terminal processor command.
The FIFO register operates bidirectionally. While its usual mode is to transfer update information from the terminal processor to the video memory, it can operate in reverse, as mentioned above, to read the contents of any video memory location back to the terminal processor for diagnostic purposes. The FIFO read mode is also used to generate a blinking cursor in each of several independent video screen display areas.